| PART |
Description |
Maker |
| QL3040-4PB456C QL3040-3PQ208I QL3040-2PB456I QL304 |
40,000 usable PLD gate pASIC 3 FPGA combining high performance and high density.
40000 usable PLD gate pASIC 3 FPGA combining High performance and high density FPGA, 1008 CLBS, 40000 GATES, 225 MHz, PBGA456
40000 usable PLD gate pASIC 3 FPGA combining High performance and high density FPGA, 1008 CLBS, 40000 GATES, 225 MHz, PQFP208
|
QuickLogic, Corp.
QuickLogic Corp.
|
| STM32F103RG STM32F103RF STM32F103RGT6 STM32F103VF |
Mainstream Performance line, ARM Cortex-M3 MCU with 1 Mbyte Flash, 72 MHz CPU, motor control, USB and CAN
XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
Mainstream Performance line, ARM Cortex-M3 MCU with 768 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
|
ST Microelectronics
STMicroelectronics
|
| QL3004 |
PLD Gate pASIC 3 FPGA Combining High Performance and High Density
|
QuickLogic Corporation
|
| QL3025 |
PLD Gate pASIC 3 FPGA Combining High Performance and High Density
|
QuickLogic Corporation
|
| TDN5-4815WI TDN5-4821WI TDN5-0910WI TDN5-0912WI TD |
The power density of high performance DC/DC converters.
|
TRACO Electronic AG
|
| MC146823 MC146823P MC146823S MC146823Z MC146823L |
High-Density High-Performance Silicon-Gate(PARALLEL INTERFACE) 24 I/O, PIA-GENERAL PURPOSE, CQCC40
From old datasheet system
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| STM32F103X810 STM32F103V8H6TR STM32F103V8H6XXX STM |
Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
|
STMicroelectronics
|
| ISPLSI1032EA-170LT100 ISPLSI1032EA-200LT100 1032EA |
60 MHz in-system prommable high density PLD
170 MHz in-system prommable high density PLD
125 MHz in-system prommable high density PLD
100 MHz in-system prommable high density PLD
Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:4 RoHS Compliant: Yes
In-System Programmable High Density PLD 在系统可编程高密度可编程逻辑器件
|
LATTICE[Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| IN74HC240ADW |
Octal 3-state inverting buffer/line driver/line receiver, high-performance silicon-gate CMOS
|
INTEGRAL
|
| IN74HCT240ADW |
Octal 3-state inverting buffer/line driver line receiver, high-performance silicon-gate CMOS
|
INTEGRAL
|
| SL74HCT241N SL74HCT241 SL74HCT241D |
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver(High-Performance Silicon-Gate CMOS)
|
System Logic Semiconduc...
SLS[System Logic Semiconductor]
|
